For more than three decades, the continued miniaturization of silicon metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. A concise summary of near-term and long-term challenges to continued complementary metal oxide semiconductor (CMOS) scaling can be found in the “Grand Challenges” section of the 2002 Update of the International Technology Roadmap for Semiconductors (ITRS). A very thorough review of the device, material, circuit, and systems can be found in Proc. IEEE, Vol. 89, No. 3, March 2001, a special issue dedicated to the limits of semiconductor technology.
Since it has become increasingly difficult to improve MOSFETs and therefore CMOS performance through continued scaling, methods for improving performance without scaling have become critical. One approach for doing this is to increase carrier (electron and/or hole) mobilities. Increased carrier mobility can be obtained, for example, by introducing the appropriate strain into the Si lattice.
The application of strain changes the lattice dimensions of the silicon (Si)-containing substrate. By changing the lattice dimensions, the electronic band structure of the material is changed as well. The change may only be slight in intrinsic semiconductors resulting in only a small change in resistance, but when the semiconducting material is doped, i.e., n-type, and partially ionized, a very small change in the energy bands can cause a large percentage change in the energy difference between the impurity levels and the band edge. This results in changes in carrier transport properties, which can be dramatic in certain cases. The application of physical stress (tensile or compressive) can be further used to enhance the performance of devices fabricated on the Si-containing substrates.
Compressive strain along the device channel increases drive current in p-type field effect transistors (pFETs) and decreases drive current in n-type field effect transistors (nFETs). Tensile strain along the device channel increases drive current in nFETs and decreases drive current in pFETs.
Strained silicon on relaxed SiGe buffer layer or relaxed SiGe-on-insulator (SGOI) has demonstrated higher drive current for both nFET [K. Rim, p. 98, VLSI 2002, B. Lee, IEDM 2002] and pFET [K. Rim, et al, p. 98, VLSI 2002] devices. Even though having strained silicon on SGOI substrates or strained silicon directly on insulator (SSDOI) can reduce the short-channel effects and some process related problems such as enhanced As diffusion in SiGe [S. Takagi, et al, p. 03-57, IEDM 2003; K. Rim et al, p. 3-49, IEDM 2003], the enhancement in the drive current starts to diminish as devices are scaled down to very short channel dimensions [Q. Xiang, et al, VLSI 2003; J. R. Hwang, et al, VLSI 2003]. The term “very short channel” denotes a device channel having a length of less than about 50 nm.
It is believed that the reduction in drive currents in very short channel devices results from source/drain series resistance and that mobility degradation is due to higher channel doping by strong halo doping, velocity saturation, and self-heating.
In addition, in the case of biaxial tensile strain, such as strained epitaxially grown Si on relaxed SiGe, significant hole mobility enhancement for pFET devices only occurs when the device channel is under a high (>1%) strain, which is disadvantageously prone to have crystalline defects. Further, the strain created by the lattice mismatch between the epitaxially grown Si atop the relaxed SiGe is reduced by stress induced by shallow trench isolation regions, wherein the effect of the shallow trench isolation regions is especially significant in the case of devices having a dimension from the gate edge to the end of the source/drain region on the order of about 500 nm or less. [T. Sanuki, et al, IEDM 2003].
Further scaling of semiconducting devices requires that the strain levels produced within the substrate be controlled and that new methods be developed to increase the strain that can be produced. In order to maintain enhancement in strained silicon with continued scaling, the amount of strain must be maintained or increased within the silicon-containing layer. Further innovation is needed to increase carrier mobility in pFET devices.